1. Field of the Invention
The present invention generally relates to semiconductor devices, and in particular, the present invention relates to a device and method for adjusting a substrate bias potential to compensate for process, activity and temperature-induced device threshold variations.
2. Description of the Related Art
FIG. 1 illustrates an example of a back-biased n-channel device. That is, in the exemplary MOS configuration of FIG. 1, the NFET 101 is a four-terminal device, and is made up of an n-region source 104, a gate electrode 103, an n-region drain 102, and a p.sup.- bulk substrate 105. The substrate or bulk 105 of the NFET 101 is biased to Vbs (as explained below) by way of a metallic back plane 106.
FIG. 2 is a circuit representation of the NFET 101 of FIG. 1. As shown, Vgs is the voltage across the gate G and the source S, Vds is the voltage across the drain D and the source S, and Vbs is the voltage across the substrate B and the source S. Reference character Id denotes the drain (or channel) current.
There are a number of factors which contribute to the magnitude of a transistor device's threshold voltage. For example, to set a device's threshold voltage near zero, light doping and/or counter doping in the channel region of the device may be provided. However, due to processing variations, the exact dopant concentration in the channel region can vary slightly from device to device. Although these variations may be slight, they can shift a device's threshold voltage by a few tens or even hundreds of millivolts. Further, dimensional variations, charge trapping in the materials and interfaces, and environmental factors such as operating temperature fluctuations can shift the threshold voltage. Still further, low threshold devices may leak too much when their circuits are in a sleep or standby mode. Thus, particularly for low-threshold devices, it is desirable to provide a mechanism for tuning the threshold voltage to account for these and other variations. This can be accomplished using back biasing, i.e. controlling the potential between a device's substrate and source. See James B. Burr, "Stanford Ultra Low Power CMOS," Symposium Record, Hot Chips V, pp. 7.4.1-7.4.12, Stanford, Calif. 1993, which is incorporated herein by reference for all purposes.
A basic characteristic of back-biased transistors resides in the ability to electrically tune the transistor thresholds. This is achieved by biasing the bulk of each transistor relative to the source to adjust the threshold potentials. In the case of bulk CMOS and partially depleted SOI devices, this means that the back bias potential is applied to the undepleted bulk material adjacent the depleted channel region of the devices. In the case of fully depleted SOI devices, this means that the back bias potential is applied to an electrode spaced from the fully depleted channel region by an insulating layer. Typically, as shown in bulk CMOS example of FIG. 1, the potential will be controlled through isolated ohmic contacts to the source and bulk regions together with circuitry necessary for independently controlling the potential of these two regions.
However, as the threshold voltage varies with temperature and other factors, there exists a need to dynamically adjust the substrate bias voltage to compensate for such temperature induced variations in device performance. Furthermore, global process variations that would otherwise shift the threshold voltage should also be compensated by applying the appropriate offset to the substrate. While various techniques are known for adjusting the substrate bias, they tend to be complex and expensive, and in some cases ineffective, particularly for low and near zero threshold voltage devices.